1. Field of the Invention
The invention relates to an improved Si-fin structure, semiconductor devices incorporating such Si-fin structures, methods of manufacturing such improved Si-fin structures and semiconductor manufacturing processes that incorporate such manufacturing methods.
2. Description of the Prior Art
Over the past 30 years, silicon-based integrated circuits and, in particular, metal-oxide-semiconductor (MOS) devices such as field effect transistors (FET or MOSFET) have consistently delivered greater speed, increased integration density and improved functionality while simultaneously reducing the cost per operation of the improved semiconductor devices. MOS devices are typically formed in a substrate 10 having heavily doped source/drain (S/D) regions 12 separated by a more lightly-doped channel region 18. The channel region 18 is, in turn, controlled by a gate electrode 14 that is separated from the channel region by a gate dielectric 16.
As the demand for speed and functional improvements continues unabated, a wide variety of structures, processes and equipment have been developed in order to provide the desired improvements. Conventional bulk-MOS techniques and designs as illustrated in FIG. 1A, are, however, approaching the practical limits of the technology and are giving rise to more complex techniques in order to control the short-channel effects and obtain useable channel lengths of 100 nm and below. These more complex techniques, however, tend to both increase the cost and decrease the yield of the resulting devices, making them less practical for general semiconductor manufacturing.
A variety of transistor designs have been proposed for overcoming certain of the deficiencies of the conventional bulk-MOS semiconductor devices including, for example, the ultra-thin body transistor, FIG. 1B, in which the channel region 18 is formed in a thin layer formed above an insulating region, and the double-gate transistor, FIG. 1C, in which a single channel region 18 is controlled by two gates 14a, 14b that are separated from the channel region by separate gate dielectrics 16a, 16b. 
FinFETs, in which the channel is formed in, the gate dielectrics are formed on, and the gate electrode is formed around a semiconductor “fin” provide structures in which the channels may be formed first, followed by the source and drain regions, a process that will tend to produce source/drain regions that are taller than the channel fin. Dielectric and conductive materials may then be sued to form what is essentially a double- or triple-gate device.
Conventional bulk-MOS devices utilize heavy channel doping to control short channel effects. These processes, however, become increasingly difficult to control as the channel length design drops below about 100 nm. Indeed, conventional bulk-MOS devices and technology, when pushed to achieve smaller critical dimensions, tend to exhibit undesirable channel mobility, subthreshold voltage instability, junction leakage, junction capacitance and current depletion.
Similarly, the ultra-thin body transistors are considerable more expensive that the conventional bulk-MOS devices to produce and, although providing improved performance in some areas, tend to exhibit characteristic electrical variations such as floating body and heat transfer effects and have current limitations imposed by the body thickness. Double-gate devices, by controlling the junction from two sides, tend to exhibit improved leakage performance, but generally necessitate the use of a complicated manufacturing process that both increases the expense and lowers the yield. The particular structures noted are not intended to be exhaustive and it is expected, therefore, that those of ordinary skill in the art will be aware of other particular constructions and/or processes that have been implemented or evaluated by various individuals or groups during efforts to address the deficiencies of the known processes and structures for manufacturing devices having channel lengths below about 100 nm.
FinFET transistors, i.e., those in which the channel is formed in a raised “fin” of semiconductor material, however, are able to provide leakage performance similar to or better than that provided by double-gate transistors, but tend to be both less complicated and less expensive to produce. FinFET transistors (or simply FinFETs) are also expected to support the scaling of channel length to below 50 nm and perhaps to about 10 nm, thereby allowing additional improvements in integration density and functional speed.
As taught in U.S. Pat. No. 6,413,802, which is incorporated herein by reference, in its entirety, FinFET devices may be manufactured from a silicon layer provided on an insulating layer, such as a buried silicon oxide (BOX) layer, that has been formed on a silicon substrate to form a silicon-on-insulator (SOI) structure. FinFETs formed in this manner, however, may remain expensive to produce, limit the degree of integration that may be achieved and suffer from variable electrical performance and/or reduced yield.
As taught in U.S. Patent Application No. 2002-0011612, which is incorporated herein by reference, in its entirety, FinFET devices may also be manufactured on a bulk semiconductor substrate. FinFETs formed in this manner, however, may result in mechanical strain and/or defects at the boundary between the fin material and the isolation oxide that will tend to increase the leakage and degrade device performance and increase the difficulty of obtaining uniform filling of the spaces between adjacent fin structures.